1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, requiring highly doped shallow junctions.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits is and will be based on silicon devices due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the huge number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence so as to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and therefore one or more anneal cycles are required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal. Moreover, besides the dopant activation and the curing of crystal damage, undesired dopant diffusion also occurs during the annealing, which may lead to a “blurred” dopant profile. With reference to FIGS. 1a-1d, a typical conventional process flow for forming a conventional field effect transistor will now be described in order to explain the problems involved in more detail.
FIG. 1a schematically shows a cross-sectional view of a transistor structure 100 at an intermediate manufacturing stage. The transistor structure 100 comprises a substrate 101, typically a silicon substrate or a substrate including a silicon layer, in which an active region 103 is enclosed by shallow trench isolations (STI) 102. A gate electrode 105 is formed over the active region 103 and is separated therefrom by a gate insulation layer 106. It should be noted that the previously mentioned gate length is, in FIG. 1a, the lateral dimension of the gate electrode 105. The portion of the active region 103 underlying the gate insulation layer 106 represents a channel region 104 disposed between source and drain extension regions 108 that may also be referred to as “tip” regions.
A typical process flow for forming the transistor structure 100 as shown in FIG. 1a may comprise the following process steps. After formation of the shallow trench isolations 102 by sophisticated photolithography, etch and deposition methods, an implantation sequence is carried out to generate a required dopant profile (not shown) within the active region 103. Thereafter, the gate insulation layer 106 is formed by advanced oxidation and/or deposition methods with a required thickness that is matched to the gate length of the gate electrode 105. Then, the gate electrode 105 is patterned from a polysilicon layer by means of advanced photolithography and etch techniques. Next, an ion implantation, indicated by reference 107, is carried out to introduce dopants of a required conductivity type into the active region 103 to thereby form the extension regions 108. As previously noted, scaling the gate length of the gate electrode 105 also requires the extension regions 108 to be provided as shallow doped regions with a depth, indicated as 109, in the range of approximately 10-100 nm for a gate length in the range of approximately 30-200 nm. Thus, the ion implantation 107 is carried out with relatively low energy, depending on the type of dopants used, and with a high dose to provide for the required high dopant concentration within the extension regions 108.
FIG. 1b schematically shows the transistor structure 100 in an advanced manufacturing stage. Sidewall spacers 110 which are typically formed of silicon dioxide or silicon nitride are formed at sidewalls of the gate electrode 105. The sidewall spacers 110 are formed by self-aligned deposition and anisotropic etch techniques in order to act as implantation masks for a subsequent ion implantation sequence 112 to form source and drain regions 111.
As previously noted, a high dopant concentration is required in the source and drain regions 111, as well as in the extension regions 108, so that severe crystal damage is generated during the implantation sequences 107, 112. Therefore, a heat treatment, such as a rapid thermal anneal, is generally required, on the one hand, to activate the dopant atoms and to substantially recrystallize the damaged structure in the source and drain regions 111 and the extension regions 108. It turns out, however, that at high dopant concentrations, the electrical activation by rapid thermal anneal cycles is limited by the solid solubility of the dopants in the silicon crystal. Additionally, the dopants readily diffuse into undesired crystalline regions of the active regions 103, thereby significantly compromising the transistor performance. On the other hand, efficiently re-establishing the crystalline structure within the source and drain regions 111 and the extension regions 108 requires relatively high temperatures over a sufficiently long time period, which may, however, unduly increase the dopant diffusion. Consequently, a trade-off is made with respect to activating and curing the transistor structure 100. Especially as device dimensions are scaled to a gate length of 100 nm and even less, the issue of degraded transistor performance due to a reduced conductivity owing to insufficiently activated dopants and/or a dopant profile blurred by diffusion is even more emphasized.
FIG. 1c schematically shows the transistor structure 100 after completion of the manufacturing process. Metal silicide regions 115 are formed on top of the gate electrode 105 and the drain and source regions 111, which may comprise cobalt silicide or any other appropriate silicide of a refractory metal. Contact lines 113 are formed in contact with the drain and source regions 111 to provide electrical contact to further circuit elements (not shown) or other interconnect lines (not shown). The contact lines 113 may typically be comprised of tungsten and other appropriate barrier and adhesion material.
Forming the metal silicide regions 115 typically involves the deposition of an appropriate refractory metal and subsequently a suitably designed anneal cycle to obtain the metal silicide regions 115 having a significantly lower sheet resistance than silicon, even when being heavily doped. Forming the contact lines 113 is carried out by depositing a dielectric layer (for convenience not shown) and patterning the same to form vias that are subsequently filled with a metal, wherein a thin barrier and adhesion layer is typically formed prior to filling in the bulk metal.
During operation of the transistor structure 100, a voltage may be applied to the contact lines 113 and a corresponding control voltage to the gate electrode 105 so that, in the case of an N-channel transistor, a thin channel forms in the channel region 104 substantially comprised of electrons, indicated by 114, wherein, as previously noted, the transistor performance, among others, significantly depends on the transition resistance from the channel 104 to the extension regions 108 and from the sheet resistance in the regions 108, since substantially no metal silicide is formed in this area. Owing to the difficulties in forming the extension regions 108 and the drain and source regions 111, i.e., insufficiently cured lattice damage and restricted concentration of activated dopants, the device performance is degraded, especially for extremely scaled transistor elements 100, thereby partially offsetting the advantages that are generally obtained by scaling the circuit elements of an integrated circuit.
In view of the above problems, there exists a need for an improved technique in forming field effect transistor structures that avoids or at least significantly reduces the problems identified above.